(1) Field of the Invention
The invention relates to a method for designing wiring topology and a fabrication method of integrated circuits including said method, and especially relates to a method for designing optimal wiring topology applied for electromigration avoidance in an integrated circuit.
(2) Description of the Prior Art
For the shrinking feature size and multiple functions of the chip, the components and the designed wires thereof disposed on the chip are more complex, so the size of the wires should be shrunk. Therefore, as the long term usage of the chip or the current density of the wire exceeding the process limitation, a mass of atoms inside of the metal wire are forced to migrate along the direction of the current, and the gradual transport eventually causes the void and the hillock formed on the wire. Said phenomenon is referred to as electromigration (EM), and the electromigration causes a permanent failure, such as open circuit or short circuit. For example, the failure of the chip is triggered when the hillock of the wire contacting with the neighbor.
The conventional method for EM avoidance essentially relies on the following two techniques: one is an accurate EM simulator for increasing the reliability; the other is a good wiring topology for EM avoidance.
The first technique is that the chip is analyzed by an accurate EM simulator at post routing for diminishing the EM risk. The narrow wire routed on the chip is widened according to the current density of the wire. However, the conventional EM fixing is applied at post-layout, which may consume tremendous routing resources and induce a large amount of layout change.
The second technique is that the good wiring topology considering EM is applied to a router, which may immune EM with much fewer routing resources. One of the conventional method for designing wiring topology is based on the Delaunay triangulation (DT) algorithm to calculate the feasible solution of the wire in advance of EM avoidance.
The DT-based method is described as below. First of all, the connected graph is constructed by the Delaunay triangulation algorithm so that each of all the source currents is connected with each of all the sink currents. Secondly, a source or a sink at the DT boundary is selected as the starting point, and the starting point is connected to the nearest neighbor in DT. Considering the two possible current directions of the connection wire, the starting point is then greedily connected to the nearest neighbor with the feasible solution and the width of the wire is determined accordingly. Another point at the DT boundary is selected to obtain the better result. Said process is repeated and, finally, the resulting tree is formed by the method for designing wiring topology with the DT-based method.
However, the tree edge is able be provided only from DT edges; thus, if the solution must include a non-DT edge, the wiring topology fails.
Consequently, how to find the optimal wiring topology to avoid electromigration and to save the routing resource is an important issue.